Selectable clock unit

ABSTRACT

The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

FIELD OF THE INVENTION

The present invention relates generally to memory devices, and morearticularly, to a memory device having a selectable clock input.

BACKGROUND OF THE INVENTION

Memory devices such as Dynamic Random Access Memories (DRAM) andsynchronous Dynamic Random Access Memories (SDRAM) are regularly used incomputing systems for applications ranging from video games to personalcomputers.

An SDRAM usually includes components such as memory arrays, row andcolumn decoders, and control logic. Additionally, an SDRAM typicallyincludes a mode register for setting an operation mode so that the SDRAMcan perform various functions that are optimally selected for the systemcontaining the SDRAM. The mode register may allow external setting ofoperation modes; that is, it may have its set values changed in responseto an externally supplied signal. An external clock signal is also usedfor memory devices to synchronize the operation of the memory devicewith other components of the computing system.

The computing systems within which SDRAMs function usually operate witha predetermined clock input which can be a single clock input or adifferential clock input. While a differential clock input system may bepreferable for characteristics such as low noise, some point to pointsystems exist where a single clock input is preferred.

To accommodate a single clock input system and a differential clockinput system, SDRAMs have to be selected according to, among otherfeatures, whether or not the SDRAM's components can accommodate theclock in the system with which the SDRAM is to be used. This need formultiple types of SDRAMs imposes not only additional manufacturing coststo produce different types of SDRAMs for various systems, but alsostorage, distribution, and other logistical costs.

What is needed is a memory device capable of accommodating more than oneclock input system, for example, a single clock input system and adifferential clock input system.

SUMMARY OF THE INVENTION

The shortcomings discussed above are largely overcome by the presentinvention which in one aspect provides a synchronous memory device witha mode register having a user selectable bit, the state of whichinternally configures the memory device to operate with either a singleclock input or a differential clock input.

In another aspect, the present invention provides a memory device whichhas a mode register in its control logic which has a user selectable bitposition which can be set to enable the control logic to appropriatelycontrol the operation of the memory device with different types ofapplied clock input signals.

In another aspect, the present invention provides a method for operatinga memory system by providing a memory controller and a memory devicehaving a mode register, initializing the memory system to operate with afirst clock input signal by sending a signal from the memory controllerto the mode register setting the memory device to operate at the firstclock input signal, and changing the memory system to operate at asecond clock input signal by sending a signal from the memory controllerto the mode register to operate the memory device at the second clockinput signal, wherein the second clock input signal is different fromthe first clock input signal.

These and other features and advantages of the present invention will bemore clearly apparent from the detailed description which is provided inconnection with accompanying drawings which illustrate exemplaryembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a portion of an SDRAM in accordance with anembodiment of the present invention;

FIG. 2 is a diagram of a computer and memory system using the SDRAMillustrated in FIG. 1;

FIG. 3 is a diagram of a control bus which may be used with the SDRAMillustrated in FIG. 1;

FIG. 4 is a diagram of a clock input;

FIG. 5 is a diagram of a mode register employed in the SDRAM shown inFIG. 1;and

FIG. 6 is diagram of another computer system in accordance with anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings, where like parts are designated by likereference numbers throughout, there is shown in FIG. 1 a simplifiedblock diagram of an SDRAM in accordance with an embodiment of thepresent invention. Although the term SDRAM is used throughout thisspecification, the present invention is applicable to any DRAMtechnology which uses a clock, and for use in any computing system suchas a game, a video card, and a computer system.

The SDRAM 10 has a control logic 20 that contains a mode register 22 anda command decoder 24. The SDRAM 10 also has a memory array 30, a rowdecoder 32 and a column decoder 34, and an address register 36. Multiplememory arrays 30 may be provided in the SDRAM 10, along with multiplerow decoders 32 and column decoders 34. A row address multiplexer 38, acolumn address counter/latch 37, and read/write data path components arealso provided within the SDRAM 10. The SDRAM 10 interfaces with externalcomponents through a control bus 50, an address bus 52, and a data bus54.

The SDRAM 10 may be used as part of a memory system 51 which in turn isused in a computing system, such as computer system 61 shown in FIG. 2.The computer system 61, which may employ multiple SDRAMs 10, has a CPU60 and a memory controller 64 which is part of memory system 51.Alternatively, the CPU 60 may provide the memory controller functions.The CPU 60 and the memory controller 64 communicate via a local bus 62.The memory controller 64, in turn, communicates with the SDRAM(s) 10 viathe control bus 50, address bus 52, and data bus 54. As illustrated inFIG. 3, the control bus 50 may include multiple signal lines, includinga row address strobe line RAS#, a clock enable line CKE, a chip selectline CS#, a write enable line WE#, and a column address strobe lineCAS#.

The control bus 50 also includes a clock signal line CK, and may includea complimentary clock signal line CK#. In a single clock input systemonly the CK signal would be present, while in a differential clock inputsystem both the CK and CK# signals would be present. Clock signals CK 72and CK# 70 are graphically represented in FIG. 4. The SDRAM 10synchronizes the output of read data with the rising edges 74 andfalling edges 76 of a single clock input system, and with the crossingpoints 78 of a differential clock input system. Differential clock inputsystems are also known as double data rate systems. The clock signalsare typically generated by a device such as an oscillator, which can belocated in a processor, in a memory controller, or anywhere else in acomputer system.

In a typical operation of the SDRAM 10, row address and column addresssignals are asserted by the memory controller 64 on the address bus 52,and latched into the address register 36. The row address signals arethen supplied to the row address multiplexer 38 which transmits the rowaddress signal to the row decoder 32, which appropriately accesses a rowof the memory array 30. The column address signals are supplied from theaddress register 36 to the column address counter/latch 37 whichtransmits the column address to the column decoder 34, whichappropriately accesses a column of the memory array 30. As stated above,if the SDRAM contains multiple memory arrays 30, multiple row decoders32 and column decoders 34 would likewise be provided.

The memory array 30 is coupled to the data bus 54 via read/write datapath circuitry 35. The read data path portion of the read/write datapath circuitry 35 comprises circuits which store output addressed dataand ensures that the proper signal levels are delivered to the data bus54. The write data path portion of the read/write data path circuitry 35comprises circuits which accept write data from the data bus 54, holddata to be written, and drive the write data to the addressed areas ofmemory array 30.

Read and write accesses to the SDRAM 10 are burst oriented, where theburst length determines the maximum number of column locations that canbe accessed for a given read or write command. In order to write data,the memory controller 64 asserts a write command on the control bus 50and subsequently supplies write data to the SDRAM 10 via the data bus54. In order to read data, the memory controller 64 asserts a readcommand on the control bus 50 while simultaneously asserting column androw addresses on the address bus 52. The preceding is a cursorydescription of the SDRAM's 10 operation; the operation may involvenumerous additional well known steps involving known components, thedescriptions of which are not provided herein for the sake of brevity.

The overall operation of the SDRAM 10 is controlled by the control logic20 which includes the command decoder 24 and the mode register 22. Thecommand decoder 24 interprets various signal combinations present on thecontrol bus 50 as high level commands asserted by the memory controller64, thereby allowing the control logic 20 to carry out internaloperations of the SDRAM 10 by implementing the asserted commands. Theoperation of the control logic 20 is further defined by the settings ofthe mode register 22, which is loaded with values which control variousSDRAM operational parameters.

The mode register 22 has bit positions which are used to define specificmodes of operation of the SDRAM 10. Binary values are set in the moderegister 22 by the memory controller 64. Typical operational stateswhich can be set by binary values set in the mode register 22 include,for example, the selection of a burst length, a burst type, and a CASlatency. The mode register 22 is typically programmed by a command fromthe memory controller 64 at initialization of the computer system 61,and will retain the stored information until it is programmed again orthe SDRAM 10 loses power. Reprogramming the mode register 22 usuallydoes not change the stored contents of the memory array(s) 30.

The mode register 22 of an SDRAM constructed in accordance with anembodiment of the present invention is illustrated in FIG. 5. The moderegister 22 has selectable bits A0-A10, BA0, and BA1 used to define thevarious modes of operation discussed above. Bit A0 defines the enable ordisable state of a delay lock loop used to synchronize initial memoryoperations, bit A1 defines the drive strength for all outputs as normalor reduced, and bits A2-A1O define various operating modes such as loadmode register, read, or write. Alternatively, bits A0-A2 may be used todefine the burst length, bit A3 may be used to define the burst type,bits A4-A6 may be used to define the CAS latency, and bits A7-A10 may beused to define the operating mode such as normal or reset operation.Although the mode register 22 illustrated in FIG. 5 contains multiplebits and sections, including an extended mode register section, the moderegister 22 in accordance with the present invention need notincorporate all those sections. These combinations and operations ofmode register bits are illustrative only and are not meant to berestrictive in order to practice the present invention.

A unique feature of mode register 22 in an SDRAM of the presentinvention is that a selectable bit may be used to define whether or notthe control logic, and therefore the SDRAM 10, will operate in a singleclock input mode or a differential clock input mode. For the exemplarymode register 22 illustrated in FIG. 5, mode register bit A10 can be setto 0 to enable the control logic 20 to operate the SDRAM 10 with asingle clock input, or set to 1 to enable the control logic 20 tooperate the SDRAM 10 within a differential clock input. As discussedabove, the SDRAM 10 synchronizes the output of read data with the risingedges 74 and falling edges 76 of a single clock input system, and withthe crossing point 78 of a differential clock input system. Either adifferential clock input or a single clock input can be the defaultsetting for the mode register 22. Although bit A10 controls the clockinput signal setting in the illustrated mode register 22, any bit may beused for this function.

The mode register 22 bit controlling the clock signal input setting forthe operation of the SDRAM 10 is usually set at initialization of thecomputer system 61 to operate in agreement with other components of thesystem. Alternatively, the mode register 22 can be switched to operatebetween different types of clock inputs after initialization of thecomputer system 61. For example, the computer system 61 may switch fromoperating at differential clock input to operating at a single clockinput when switching from a regular mode to a power savings mode, orfrom a regular mode to a test mode. During a power savings mode, it maybe advantageous to shut down several components of computer system 61,but to retain the memory stored in the SDRAM 10. For this purpose, asignal may be sent to the memory controller 64 to set the mode register22, and thereby the control logic 20, to operate at a single clockinput, thereby decreasing the amount of power consumed by the computersystem 61 and SDRAM memory device. When the computer system 61 is toreturn to a normal operating mode, a signal would be sent to the memorycontroller 64 to reset the mode register 22 and control logic 20 tooperate with a differential clock input system.

FIG. 6 illustrates an example of a computer system 80 that mayincorporate an SDRAM 10 containing a mode register 22 in accordance withthe present invention. The system 80 has a memory circuit 82 includingan SDRAM 10 constructed in accordance with the present invention. Thecomputer system 80 includes a central processing unit (CPU) 84 forperforming computer functions, such as executing software to performdesired tasks and calculations. One or more input/output devices 86, 88,such as a keypad or a mouse, are coupled to the CPU 84 and allow anoperator to manually input data thereto or to display or otherwiseoutput data generated by the CPU 84. One or more peripheral devices suchas a floppy disk drive 90 or a CD ROM drive 92 may also be coupled tothe CPU 84. The computer system 80 also includes a bus 94 that couplesthe input/output devices 86, 88 and the memory circuit 82 to the CPU 84.

Thus, the present invention provides a mode register 22 that can enableone SDRAM 10 to operate with both single clock and differential clockinput systems. This reduces the need to stock multiple types of SDRAMs,thereby reducing costs associated with manufacturing and stockingmultiple types of components. Additionally, the mode register 22 inaccordance with the present invention allows for the SDRAM 10 to operatein a computing system designed to switch between differential clock andsingle clock input signals.

While the foregoing has described in detail preferred embodiments knownat the time, it should be readily understood that the invention is notlimited to the disclosed embodiments. For example, although theinvention has been described with respect to switching SDRAM operationbetween a single clock input or a differential clock input, it should beapparent that the invention can also be implemented with a suitable moderegister input to select among any two or more different types of clockinputs. In addition, the invention can be modified to incorporate anynumber of variations, alterations, substitutions or equivalentarrangements not heretofore described, but which are commensurate withthe spirit and scope of the invention. Accordingly, the invention is notlimited to the embodiment specifically described but is only limited bythe scope of the appended claims.

1-32. (canceled)
 33. A memory device comprising: an input for receivinga clock signal having a specified frequency; and a mode register havingat least one programmable storage location for storing informationidentifying a type of clock input signal which will be used duringoperation of said memory device in one of a regular mode and a powersaving mode.
 34. The memory device according to claim 33 wherein saidprogrammable storage location has a default setting for one type ofclock input signal.
 35. The memory device according to claim 34 whereinsaid one type of clock input signal is a single clock input signal. 36.The memory device according to claim 34 wherein said one type of clockinput signal is a differential clock input signal.
 37. The memory deviceaccording to claim 33 wherein said programmable storage location storesinformation indicating at least one of a first type of clock inputsignal and a second type of clock input signal.
 38. The memory deviceaccording to claim 33 wherein in said power saving mode an amount ofpower used by said memory device is less than in said regular mode. 39.A computing system comprising: a processor; and a memory device incommunication with said processor, said memory device comprising a moderegister having bits for setting operational parameters for said memorydevice, wherein at least one of said bits is capable of being set toidentify a clock input signal which will be used during operation ofsaid memory device in either a regular mode or a power saving mode. 40.The computing system according to claim 39 wherein in said power savingmode an amount of power used by said computing system is less than insaid regular mode.
 41. The computing system according to claim 39wherein said clock input signal is a single clock input signal.
 42. Thecomputing system according to claim 39 wherein said clock input signalis a differential clock input signal.
 43. A control circuit for a memorydevice, comprising: a mode register having at least one programmablestorage location for storing information identifying a type of clockinput signal which will be used during operation of a memory device ineither a regular mode or a power saving mode; and a logic circuitresponsive to contents of said mode register for operating said memorydevice in either said regular mode or said power saving mode.
 44. Thecontrol circuit according to claim 43 wherein said programmable storagelocation has a default setting for one type of clock input signal. 45.The control circuit according to claim 44 wherein said one type of clockinput signal is a single clock input signal.
 46. The control circuitaccording to claim 44 wherein said one type of clock input signal is adifferential input signal.
 47. The control circuit according to claim 43wherein in said power saving mode an amount of power used by saidcontrol circuit is less than in said regular mode.
 48. The controlcircuit according to claim 43 wherein said programmable storage locationstores information indicating at least one of a first type of clockinput signal and a second type of clock input signal.
 49. The controlcircuit according to claim 48 wherein said first type of clock inputsignal is a single clock input signal and said second type of clockinput signal is a differential clock input signal.
 50. The controlcircuit according to claim 43, wherein said memory device is capable ofoperating in response to more than one clock input signal.
 51. A methodof operating a computing system comprising: providing a clock signalgenerating device in communication with a memory device, wherein saidmemory device is programmed to operate in either a regular mode or apower saving mode according to a clock input signal from said clocksignal generating device, and wherein said memory device has a moderegister having a storage location for storing information identifying atype of clock input signal.
 52. The method according to claim 51 whereinsaid clock input signal is a single clock input signal in said powersaving mode.
 53. The method according to claim 51 wherein said clockinput signal is a differential clock input signal in said regular mode.54. A method for operating a memory system comprising: providing amemory controller and a double data rate memory device having a moderegister; initializing said memory system to operate in a regular modeat a first clock input signal by sending a first signal from said memorycontroller to said mode register setting said double data rate memorydevice to operate at said first clock input signal and storinginformation identifying said first clock input signal in said moderegister; and changing said memory system to operate in a power savingmode at a second clock input signal by sending a second signal from saidmemory controller to said mode register to operate said double data ratememory device at said second clock input signal and storing informationidentifying said second clock input signal in said mode register,wherein said second clock input signal is different from said firstclock input signal.
 55. The method according to claim 54 wherein saidfirst clock input signal is a differential clock input signal.
 56. Themethod according to claim 54 wherein said second clock input signal is asingle clock input signal.